1. Field of the Invention
This invention relates in general to the field of segment register and offset loading and more particularly to an improved method and apparatus for fast loading of a selector/offset pointer.
2. Description of the Related Art
Within computer systems, microprocessors are used to execute instructions that operate on data stored in memory. Retrieval of instructions, and retrieval and storage of data is performed by reading from and writing to particular memory locations. The particular memory locations each have an address that is designated by the microprocessor at the time of a read or a write operation.
Within x86 computer systems, memory is often divided into a number of different memory segments, each having its own set of privileges and characteristics. This is referred to as memory segmentation. An example of a segmented memory 100 is provided in FIG. 1, where a physical memory 102 is divided into a number of different memory segments 104, 106, 108 and 110. The memory segments are accessed by referencing one of a plurality of segment registers 112 as an operand in a processor instruction, either explicitly or implicitly. The segment registers 112 contain a 16-bit selector that references a particular descriptor 114. The descriptor 114 defines the attributes of a memory segment, including a base address 116 for a memory segment. Particular memory locations within a memory segment are then determined by specifying an offset from the base address as a second operand.
One scheme that has been developed to access particular memory locations utilizes a pointer to define an address for a memory location. A pointer is a data type that contains a value that gives the address of a datum within a memory location. Pointers are useful for building complex data structures such as lists and trees that vary dramatically in structure as a program executes. Each element in a list or tree structure contains one or more pointers to other elements, so that elements can be linked and unlinked simply by storing addresses of other elements in these pointers.
Referring to FIG. 2, two types of pointers are shown. The first type is a 48-bit full pointer that contains a two-part address. The offset part 202 is in the low-order 32-bits, and the segment selector 204 is in the high order 16-bits. To address data with a 48-bit pointer, the two parts must be loaded into registers within a microprocessor. The segment selector 204 in the high order 16-bits is loaded into one of the segment registers (shown below in FIG. 3). The offset part 202 in the low-order 32-bits is loaded into one of the general registers of a microprocessor (not shown). If all the addresses to be stored in pointers have the same segment part, a selector is stored in a dedicated segment register, and only the offsets are provided as operands in instructions.
As was mentioned above, to reference a particular memory location using a pointer, the pointer must first be loaded into a segment register/general register pair within a microprocessor. A macro instruction 300 that performs this load operation is shown in FIG. 3.
The macro instruction 300 contains an opcode 302 that specifies the instruction as a pointer load instruction, and specifies the segment register to be loaded. In FIG. 3, the DS segment register has been designated. If one of the other segment registers 112 illustrated in FIG. 1 are to be loaded with a pointer, that segment register would be specified in the opcode 302, accordingly.
Within the load pointer instruction 300, an operand 304 is also specified, that indicates the general purpose register that should be loaded with the 32-bit base address. In FIG. 3, the CX register has been designated. However, one skilled in the art will appreciate that one of the other general purpose registers may be specified.
Finally, a memory address 306 is provided that stores the 48-bit pointer to be loaded. The double word found at mem48 is loaded into the general purpose register 304, and the word found at mem48+4 is loaded into the segment register specified by opcode 302. Once the 48-bit pointer has been loaded into the segment register/general register pair, the pointer may be used to access memory.
When loading a segment register/general register pair, it is common to first load the offset into a temporary register, to then load the segment register, and only after the segment register load has been completed, to move the offset into the general purpose register. For reasons known to those skilled in the art, it is possible that the segment register load operation may fail. For a background on the details of segment register loading, and exception conditions that may be created during a segment load, attention is directed to U.S. Pat. No. 4,442,484 entitled "MICROPROCESSOR MEMORY MANAGEMENT AND PROTECTION MECHANISM" which is hereby incorporated by reference.
The commonly used load sequence is important. If the general purpose register is overwritten with the offset before the segment register has been loaded, and the segment register load fails, the contents of the general purpose register will be incorrect. In addition, once overwritten, the microprocessor is unable to restore the general purpose register to its previous condition. That is why all known microprocessors store the offset into a temporary register, and do not overwrite the general purpose register, until after the segment load has completed.
A problem with the prior art sequence is that additional processing time is required to first load the offset into a temporary register, and later transfer the contents of the temporary register into the general purpose register. If it is presumed that each step in the above described sequence requires a single clock cycle, then at least 25% of the instruction sequence is required, just to ensure that the general purpose register is not overwritten prior to a successful segment load.
What is needed is an apparatus and method that improves the execution of a pointer load operation. More specifically, what is needed is an apparatus and method that stores the offset directly into the general purpose register, but provides a mechanism for restoring the general purpose register if the segment load fails.